1. Field of the Invention The present invention relates generally to memory systems and, more particularly, to reconfigurable memory systems including a variably sized page-accessed data memory portion and a variably sized, simultaneously accessible, word-accessed, cache status memory portion.
2. Related Art
In complex computing environments, difficult computing tasks may be divided into sub-tasks for parallel processing by multiple processors. Typically, at least one processor is designated as a scheduling processor for scheduling tasks to be performed by the other processors.
In a multi-processing system, individual processors may be provided with local memory for storing necessary data and applications software for processing assigned tasks. Often, one processor has access to data and applications software for performing one or more specific type or group of specific types of tasks while other processors have access to different data and software applications programs for performing other types of tasks. This type of system permits specialization of processors and division of labor according to the type of task to be performed.
One drawback of a specialized multi processing system is that where a series of similar tasks must be performed, one or more processors may lack the necessary data or software for processing those tasks. As a result, one or more processors may sit idle while others struggle to process the tasks alone.
In more advanced multi-processing systems, a shared memory is provided for storing necessary data and software for performing one or more anticipated tasks. A shared memory is accessible by most, if not all, processors or requesters within the system so that each processor is capable of performing any assigned task. A central controller or scheduler divides the tasks equally among all processors, thus insuring that the tasks are completed as quickly as possible.
In a shared memory system, however, conflicts may arise if different processors or requestors attempt to access the same location of shared memory. A shared memory system must, therefore, include a conflict resolution method for determining which requestor should be granted access. A conflict resolution device may at times, have to provide a particular requestor with sole access to the requested memory location. Sole access may be required where a processor is assigned a task which requires repeated access to specified data or applications software, especially where the requestor may change the value stored in the shared memory.
A typical method of restricting access to specified memory locations is to assign ownership of individual memory locations to particular requestors. A simple ownership scheme may provide only one level of ownership. In such a system, if a requestor has ownership over a particular memory location, it has full authority to access, i.e., read from or write to, that location and no other processor is permitted access to that location. More complicated ownership schemes may provide multiple levels of ownership, each higher level providing a higher degree of control. Multiple levels of ownership may be based on priority levels assigned to individual requestors or other factors.
Regardless of the specific type of ownership protocol employed, a shared memory system must provide for storing and updating ownership data.
Typically, ownership data is stored in a reserved portion of the memory which it tracks. The ownership-storing portion of memory is often referred to as cache-status memory or status memory while the tracked-memory is typically referred to as data memory. Because each successive group of data memory words comprising a cache page, typically four words, requires an associated status data location for storing status data associated with the cache page data, a substantial portion of memory must be reserved for status data.
A second problem encountered in shared memory systems concerns reading and updating cache status memory. Typically, when a memory controller accesses data memory, it must also read the associated cache status memory. This is to insure that ownership rules are not violated and to determine whether ownership status must be updated for that location. If ownership data requires updating, then the memory controller must also write to the cache status memory.
One method of maintaining ownership in a shared memory system is to employ a Read-Modify-Write sequence concurrently for data and status. With this method, every memory access includes reading a data location and an associated cache location, modifying the cache status, and then writing the modified cache status back to the cache status memory, and writing the data back to the data memory. Thus, when data must be written, a data read is unnecessarily performed when status is read. Similarly, when data must be read, an unnecessary data write is performed when status is written.
Yet a further drawback to typical shared memory systems is their inability to accommodate multiple or various memory configurations. Multi-processor systems are employed for a variety of different types of tasks, some of which are unforeseen at the time of manufacture. Some tasks may be memory intensive, requiring vast amounts of memory for storing data or applications, while other tasks may be speed or space sensitive, where only minimal memory capacity is desired. Typical multi-processor systems, however, incorporate fixed designs with little ability for memory reconfiguration.
This is due, in part, to memory controllers which generate addressing, timing and control signals for the data and cache status memories. These memory controllers are typically designed for specific memory devices having a specified memory size and addressing scheme. Once a memory controller is chosen for incorporation into a memory system, the memory system is limited to employing only memory devices which are compatible with the provided memory controller.
A shared memory system, therefore, generally requires substantial cache memory space for storing the status of associated data, performs unnecessary data read and write cycles and does not sufficiently provide for memory reconfiguration capabilities. These drawbacks may, in some circumstances, outweigh the advantages of sharing memory.
What is needed, therefore, is a reconfigurable memory system including a page accessed data memory portion and a word accessed cache status memory portion which are simultaneously but independently accessed.